1. Field of the Invention
The present invention relates to a semiconductor device for driving liquid crystals, that installs a memory for storing display-data such as data to be displayed and to a liquid crystal display apparatus.
2. Discussion of the Background
Liquid crystal display apparatuses have been drawing the attention for being used as light-weight and lower-power consuming flat displays.
Shown in FIG. 5 is a block diagram of a liquid-crystal display apparatus that installs a RAM (Random Access Memory) as a display-data memory.
The liquid crystal display apparatus is provided with a liquid crystal displaying section 2, a common-electrode driver 40, a segment-electrode driver 45 and a display-data RAM 50.
The liquid crystal displaying section 2 is a simple matrix type equipped with a first transparent substrate on which common electrodes are arranged in parallel and a second transparent substrate on which segment electrodes are arranged in parallel.
The first and the second transparent substrates face each other so that the segment and common electrodes cross each other, with a liquid crystal layer interposed therebetween.
A scanning line COMi (i=1, . . . , m) is connected to each common electrode. Moreover, a signal line SEGj (j=1, . . . , n) is connected to each segment electrode.
One of the scanning lines is selected by the common-electrode driver 40 to drive a common electrode connected to the selected scanning line.
Data to be displayed stored in the display-data RAM 50 are retrieved by the segment-electrode driver 45 and supplied to the corresponding segment electrodes via the signal lines.
The segment-electrode driver 45 and the display-data RAM 50 are fabricated on one chip, which is called a liquid crystal-driving semiconductor device.
A known liquid crystal-driving semiconductor device is shown in FIG. 6. The known device is provided with the segment-electrode driver 45 and the display-data RAM 50.
The display-data RAM 50 is provided with a cell array 51 on which RAM cells 52 are arranged in a matrix, an address decoder 55, a display-data read counter/decoder 57, an I/F (interface) controller 60, a data I/O circuit 62 and an oscillator 65. Each RAM cell 52 consists of two transistors, a latch circuit having two inverter gates, and a three-state driver.
The display-data RAM 50 shown in FIG. 6 is therefore a dual-port RAM 50 in which each RAM cell 52 has ten transistors.
When a CPU (not shown) has access to the display-data RAM 50, it sends an I/F signal to the I/F controller 60. On receiving the signal, the I/F controller 60 drives the address decoder 55 and the data I/O circuit 62.
An address decided by the CPU is input to the address decoder 55 via an address bus and decoded, so that the corresponding RAM cell 52 is selected on the display-data RAM 50.
Data programming is performed such that data sent on the data bus is programmed into the selected cell on the display-data RAM 50 via the data I/O circuit 62.
Data retrieval is performed such that data is retrieved from the selected cell on the RAM 50 and sent to the data bus via the data I/O circuit 62.
Data transfer to the liquid crystal displaying section 2 is performed such that the oscillator 65 sends a clock signal to the display-data read counter/decoder 57. On receiving the clock signal, the counter/decoder 57 sends a selection signal to the RAM 50. Data is then retrieved from the corresponding RAM cell 52 and stored in the segment driver 45 in response to a latch signal output by the counter/decoder 57.
The known liquid crystal-driving semiconductor device shown in FIG. 6 has a display-data output port and a CPU-access input/output port separately, so that the CPU can have an asynchronous access to the RAM 50.
The known device however requires ten transistors for each RAM 52 because the display-data RAM is a dual-port RAM, thus becoming large in its chip size.
FIG. 7 shows another known liquid crystal-driving semiconductor device for which the chip-size problem has been solved.
The known device shown in FIG. 7 is provided with a display-data RAM 50A of the same type as the display-data RAM 50 (FIG. 6) except that the RAM 50A has two transistors and two inverter gates for each RAM cell 53. The display-data RAM 50A is therefore a single-port RAM 50A. The known device in FIG. 7 is also provided with a segment-electrode driver 46.
Each memory cell 53 has six transistors, so that the chip size for the single-port RAM 50A is smaller than the known liquid crystal-driving semiconductor device shown in FIG. 6.
In the known liquid crystal-driving semiconductor device shown in FIG. 7, however, the RAM 50A has a single port that is used as a display-data output port and also as a CPU-access input/output port, so that a CPU can not have an asynchronous access to the RAM 50A.
When a CPU (not shown) tries to have access while the liquid crystal displaying section is to retrieve data from the RAM 50A, either the CPU or the displaying section has the priority whereas the other has to wait.
The liquid crystal displaying section retrieves data on a constant cycle. When the CPU has the priority, it programs data on the RAM 50A while this data has remained in the CPU-access input/output port that is the display-data output port.
This results in that, when the liquid crystal displaying section retrieves display-data from the RAM 50A, the data that has been programmed by the CPU is retrieved as the display-data. This data is different from the data to be displayed and also has no correlation with data now on display. And, if displayed, this data causes flicker on screen, thus degrading picture quality.
On the other hand, when the liquid crystal display has the priority, the CPU takes long for data programming to the RAM 50A.